This invention is in the field of solid-state memory. Embodiments of this invention more specifically pertain to the programming and reading of one-time programmable non-volatile memory.
Non-volatile solid-state read/write memory devices are commonplace in many modern electronic systems, particularly in portable electronic devices and systems. Conventional types of non-volatile solid-state memory devices include those referred to as electrically programmable read-only memory (EPROM) devices. Modern EPROM memory cells include one or more “floating-gate” transistors that store the data state. In a general sense, these floating-gate transistors are “programmed” by the application of a bias that enables holes or electrons to tunnel or be injected through a thin dielectric film onto an electrically isolated transistor gate element, which is the floating gate of the transistor. This trapped charge on the floating gate will modulate the apparent threshold voltage of the memory cell transistor, as compared with the threshold voltage with no charge trapped on the floating gate. This difference in threshold voltage can be detected by sensing the resulting difference in source-drain conduction, under normal transistor bias conditions, between the programmed and unprogrammed states. Some EPROM devices are “erasable” in that the trapped charge can be removed from the floating gate, for example by exposure of the memory cells to ultraviolet light (such memories referred to as “UV EPROMS”) or by application of a particular electrical bias condition that enables tunneling of the charge from the floating gate (such memories referred to as electrically-erasable or electrically-alterable, i.e., EEPROMs and EAPROMS, respectively). “Flash” memory devices are typically realized by EEPROM memory arrays in which the erase operation is applied simultaneously to a “block” of memory cells.
Because of the convenience and efficiency of modern EPROM and EEPROM functions, it is now commonplace to embed non-volatile memory arrays within larger scale integrated circuits, such as modern complex microprocessors, digital signal processors, and other large-scale logic circuitry. Such embedded non-volatile memories can be used as non-volatile program memory storing software routines executable by the processor, and also as non-volatile data storage. On a smaller scale, non-volatile memory cells can realize control registers by way of which a larger scale logic circuit can be configured, or can be used to “trim” analog levels after electrical measurement.
As known in the art, “one-time programmable” (“OTP”) memories are also popular, especially in embedded non-volatile memory applications as mentioned above. The memory cells of OTP memories are constructed similarly or identically as UV EPROM cells, and as such are not electrically erasable. But when mounted in an opaque package, without a window through which the memory can be exposed to ultraviolet light, the UV EPROM cells may be programmed one and only one time. In embedded applications, OTP memories are useful for storing the program code to be executed by the embedding microcontroller or microprocessor.
FIG. 1 illustrates the construction of conventional non-volatile memory cell 5j,k, which resides in a row j and column k of an EPROM array. In this example, cell 5j,k includes p-channel metal-oxide semiconductor (MOS) select transistor 2, p-channel MOS floating-gate transistor 4, and n-channel MOS precharge transistor 6, with their source-drain paths connected in series between a high bias voltage Vhi and a low bias voltage Vlo (which may be at ground, for example). The gate of transistor 2 receives word line WLj* for the row j in which cell 5j,k resides (and which is a negative logic signal, as indicated by the *), and the gate of transistor 6 receives precharge signal PCHG. The gate of floating-gate transistor 4 is left floating in this example. Sense node SN is at the common drain node of transistors 4 and 6, and is connected to read amplifier 8 (either directly, or via select circuitry). In this example, read circuit 8 includes a buffer and Schmitt trigger in series, but may alternatively be arranged in any one of a number of known configurations.
Floating-gate transistor 4 is programmable by the application of a particular bias condition to its source and drain to cause electrons or holes to tunnel or be injected from the source or drain of transistor 4 into its floating gate electrode, and become trapped there. In some instances, the gate of select transistor 2 physically overlies, at least in part, the gate of floating-gate transistor 4 (e.g., in a “split-gate” arrangement), such that its voltage also plays a role in the programming mechanism. In UV EPROMs (and OTPs), the trapped charge will remain at the floating gate electrode indefinitely, subject to leakage or until photoelectrically recombined. In electrically erasable memories, an erase electrode (not shown in FIG. 1) provides the necessary bias for reverse tunneling of the trapped charge. In either case, the trapped charge modulates the threshold voltage of transistor 4, typically in a binary sense so that transistor 4 either conducts or does not conduct upon select transistor 2 being turned on. In the particular example of FIG. 1, p-channel floating gate transistor 4 is considered programmed to a “1” data state if electrons are trapped on its floating gate electrode as a result of the programming operation. In this “1” programmed state, transistor 4 will conduct if it conducts with the application of a negative drain-to-source voltage. Conversely, the “0” data state corresponds to electrons not being trapped on the floating gate electrode of transistor 4, such that transistor 4 does not conduct with the application of a negative drain-to-source voltage.
In operation, the read cycle for cell 5j,k begins with precharge signal PCHG being driven active high, which turns on precharge transistor 6; select transistor 2 is held off during this precharge operation, by word line WLj* being inactive at a logic high level. This operation discharges sense node SN to voltage Vlo, following which precharge signal PCHG is driven inactive low to isolate sense node SN from voltage Vlo. The read of the state of floating-gate transistor 4 is then accomplished by word line WLj* being driven active to a logic low level, for example in response to a memory address selecting row j in which cell 5j,k resides. Select transistor 2 is turned on by word line WLj* driven low, placing a high voltage Vhi (less any voltage drop across transistor 2) at the source of floating-gate transistor 4. If floating-gate transistor 4 has been programmed to its “1” state (i.e., electrons are trapped at its floating gate electrode, reducing the threshold voltage of the device), the negative drain-to-source voltage across transistor 4 will result in source/drain conduction, pulling the voltage at sense node SN high toward voltage Vhi. Conversely, if floating-gate transistor 4 is left in its unprogrammed “0” state (i.e., electrons are not trapped at its floating gate electrode), it will remain nominally non-conductive and sense node SN will remain at its discharged low level. In either case, the state of sense node SN will be communicated via read amplifier 8 to terminal D_OUT, and communicated externally from the memory in the conventional manner.
As known in the art, memory cells 5 including floating-gate transistors 4 are programmed by the application of a relatively high voltage differential across its terminals. In the particular case shown in FIG. 1, in which transistor 4 does not include a control gate or other terminal that establishes a gate voltage during programming, transistor 4 is programmed by the application of a relatively high source-drain voltage differential. For example, if p-channel transistor 4 is in its erased state, in which it does not conduct upon application of a nominal drain-to-source voltage for read cycles, transistor 4 will be programmed by applying a drain-to-source voltage high enough, and for a sufficient duration (typically a series of pulses) that electrons become trapped on its floating-gate electrode; enough trapped electrons will shift the threshold voltage sufficiently so that transistor 4 conducts upon application of the nominal read cycle drain-to-source voltage. In modern floating-gate non-volatile memory cells, the programming time for a single memory cell 5 is on the order of 200 μsec. Even if a number of cells are programmed simultaneously, the time required to program a memory of significant size can be significant.
The manufacture of integrated circuits including non-volatile memories, including one-time-programmable memories, requires testing of the integrated circuits to ensure that any data pattern can be programmed to and read from the memory array. For those one-time programmable memories that are UV-erasable, a typical manufacturing test flow performed on devices in wafer form will include programming several different data patterns (diagonal, checkerboard, all ones, etc.), and corresponding read cycles to verify the programmed data, in order to screen out those memory cells and devices that may suffer from various defects, including those that are pattern dependent. These programming steps are then followed by UV-erase. In many cases, the memory manufacturer also programs the finished one-time programmable memory (i.e., as packaged) with the customers' desired data pattern. As a result, it is common for the test flow of one-time programmable memories to include three, four, or even more programming operations. Given the relatively long programming time mentioned above, the manufacturing test time associated with these programming operations can be significant, as can the testing cost considering the high cost of modern integrated circuit test equipment.
By way of further background, the architectures of some non-volatile memories include column select circuitry that, in each read cycle, select which of the bit lines in the array are to be sensed by the read amplifiers based on the column address applied to the memory. For example in such an architecture, if the memory array includes 128 bit lines in each row (i.e., 128 memory cells are selected by the selected word line in each read cycle), the column select circuitry may include a hierarchy of multiplexers to select the desired number of bit lines (e.g., eight bit lines to read a data byte) according to the column address. These multiplexers in the column select circuitry necessarily present significant parasitic resistance and capacitance to the relatively weak bit line signal, which reduces read performance.